It is generally believed that single-walled carbon nanotubes (CNTs) can produce integrated circuits less than 10nm, but this will require scalable production of compact and electronic pure semiconductor nanotube arrays on chips. Therefore, Professor Peng Lianmao and Professor Zhang Zhiyong (co-communication author) of Peking University have developed a multi-dispersion and sorting process, A self-alignment (DLSA) program with extremely high semiconductor purity and size limitation has been obtained, which is prepared on a 10cm silicon wafer and arranged neatly, CNT array with adjustable density of 100 to 200 CNTs per Micron. At the same time, the top gate field effect transistor (FETs) prepared on the CNT array shows better performance than the commercial silicon oxide semiconductor FET with similar gate length, in particular, the conduction current is 1.3 mA/μm, and the record transconductivity is 0.9mS. At the same time, the ion-liquid gate is used to keep the threshold swing less than 90mV/10 years at low room temperature, the maximum oscillation frequency of the top gate five-stage ring oscillator prepared in batches is greater than 8 GHz. The related paper, entitled "Aligned, high-densitysemiconducting carbon nanotube arrays for high-performance electronics", was published on the Science on May 22, 2020.
Paper link
https://science.sciencemag.org/content/368/6493/850
The development of modern integrated circuits (IC) requires proportional scaling of field effect transistors (FETs) to provide higher density, performance and energy efficiency. Ultra-thin semiconductor channels with high carrier mobility can minimize short channel effect in actively expanding FETs. The energy efficiency of single-walled carbon nanotubes (CNTs) is 10 times that of traditional complementary metal oxide semiconductor (CMOS)FET, because electronic transmission is ballistic and has excellent electrostatic performance. In addition, prototype transistors constructed on independent CNTs (gate length as short as 5 nm) are superior to Si CMOS transistors in inherent performance and power consumption. However, Si CMOS FETs with actual performance exceeding CNT FETs have not been realized in similar technologies, and the CNTs materials used by them are still far from suitable for electronic products. As the cornerstone of high-performance digital electronic products, ultra-large-scale CNT FETs should include multiple semiconductor CNTs in the channel to provide sufficient driving capability, semiconductor CNT arrays with high density arrangement are required as Channel materials for manufacturing large-scale IC.
In this paper, according to a series of spectral characteristics and electrochemical test results, the author reported a multi-dispersion sorting process, and obtained a diameter distribution of 1.45±0.23nm, electric measurement of 1300 field effect tubes containing at least 2 million CNTs in CNTs solution with semiconductor purity> 99.9999%. At the same time, a self-alignment (DLSA) program with limited size was developed to prepare a well-arranged CNT array on a 4-inch (10cm) wafer, its adjustable density range is 100 to 200CNTs /μm, which meets the basic requirements of CNTs for large-scale (but non-industrial) integrated circuit manufacturing. A- CNT array of FET and integrated circuits optimized based on DLSA processing structure and process show better performance than traditional Si CMOS transistors.
Figure 1. Transistor structure and goals to be achieved based on CNT FET digital IC technology
FIG. 2. Preparation and characterization of A- CNT array
Figure 3. Characteristics and benchmarks of top grid PETs based on A- CNT array
Figure 4. Ion-liquid grid CNT array FETs
Figure 5. Structure and characteristics of CNT five-level ROs
In a word, the author found good arrangement, high purity (better than 99.9999%) and high density (adjustable between 100 and 200CNTs /μm) by combining multiple dispersion sorting and DLSA method. The array CNTs can be prepared on 4-inch silicon wafer with complete wafer coverage rate; These CNT arrays meet the basic requirements of large-scale digital IC manufacturing. The preliminary demonstration of CNT arrays prepared by DLSA shows that the performance of these CNT arrays FETs and integrated circuits in several key performance indexes is better than that of silicon technology with similar characteristic lengths. (Text: Caspar)
